Notes on the SWIM controller chip.
Alastair Bridgewater, Febuary 2, 2001.

The SWIM drive controller chips used in such Macs as the Classic and the
IIcx are descended from the original Disk ][ drive controller card for
the Apple ][ series of computers. Unlike the previous generation drive
controller (the IWM controller), they support both GCR and MFM format
disks. They also support two sets of registers, although only one set
may be used at a time (see Switching between IWM and SWIM modes below).


SWIM mode register layout:

	.equ	writeData,	0x0000	/* Data (write) */
	.equ	writeMark,	0x0200	/* Mark (write) */
	.equ	writeCrc,	0x0400	/* CRC (write) */
	.equ	writeParameter,	0x0600	/* Parameter data (write) */
	.equ	writePhase,	0x0800	/* Phase (write) */
	.equ	writeSetup,	0x0a00	/* Setup (write) */
	.equ	modeZeros,	0x0c00	/* mode register zeros (write) */
	.equ	modeOnes,	0x0e00	/* mode register ones (write) */

	.equ	???		0x1000	/* ??? (read?) */ /* data read? */
	.equ	readData,	0x1200	/* Data (read) */ /* mark read? */
	.equ	???		0x1400	/* ??? (read) (error?) (mark?) */
	.equ	readParameter,	0x1600	/* Parameter data (read) */
	.equ	readPhase,	0x1800	/* Phase (read) */
	.equ	readSetup,	0x1a00	/* Setup (read) */
	.equ	readMode,	0x1c00	/* mode register (read) */
	.equ	handshake,	0x1e00	/* Handshake (read) */

According to the patent (US4916556), the SWIM chip has 16 registers as
follows: data (r/w), mark (r/w), error (r), write CRC (w), parameter data
(r/w), phase (r/w), setup (r/w), handshake (r), mode zeros (w), mode ones
(w), and status (r).


Switching between IWM and SWIM modes:

To switch from SWIM mode to IWM mode, clear bit 6 of the mode register by
writing 0x40 (or any other value with that bit set) to modeZeros. Typically,
this value will be 0xf8, to clear the action, writemode, HEDSEL, and MOTORON
bits at the same time.

To switch from IWM mode to SWIM mode, use the following code fragment:

	tstb	a0@(q7L)
	tstb	a0@(mtrOff)
	tstb	a0@(q6H)
	moveb	#0x57,d2
	moveb	d2,a0@(q7H)
	moveb	#0x17,a0@(q7H)
	moveb	d2,a0@(q7H)
	moveb	d2,a0@(q7H)

To determine which mode the chip is in, store data in writePhase, and see
if it shows up in readPhase (it will if the chip is in SWIM mode). The
sequence of values used for this in the Classic's .Sony driver is 0xf5,
0xf6, 0xf7.


Selecting a drive:

Bits one and two of the mode register select the internal and external
drives, respectively, and bit 7 controls the motoron signal.


Manipulating the disk Phase and SEL lines, and reading the SENSE line:

Disk phase lines are controlled by means of the phase register. The bottom
four bits control the state of their respective phase lines. The top four
bits are usually all set to 1 to indicate that the phase lines are all
outputs.

While the patent appears to indicate that the disk SEL line can be
controlled by the SWIM chip (and the SWIM III driver in MkLinux concurs),
the SEL line is still controlled by the VIA in both the IIcx and Classic
.Sony drivers.

The sense line can be read by way of bit three of the handshake register.


Parameter memory:

The SWIM chip has 16 bytes of parameter memory. This memory is accessed by
successive accesses to the parameter register (either read or write). The
offset into parameter memory for the next access can be reset by writing to
the modeZeros register.


EOF