![[ICO]](/theme/icons/blank.png){kind=icon} | Name | Last modified | Size |
|---|---|---|---|
![[PARENTDIR]](/theme/icons/folder-home.png){kind=icon} | Parent Directory | - | |
![[DIR]](/theme/icons/folder.png){kind=icon} | CPLD/ | 2023-09-27 00:34 | - |
| CPU/ | 2023-09-27 00:35 | - |
| DRAM/ | 2023-09-27 00:36 | - |
| Flash RAM/ | 2023-09-27 00:36 | - |
| FPGA/ | 2023-09-27 00:36 | - |
| Glue Logic/ | 2023-09-27 00:37 | - |
| Interface Adapters/ | 2023-09-27 00:37 | - |
| Micro Controller/ | 2023-09-27 00:37 | - |
| PIC/ | 2023-09-27 00:37 | - |
| Pics/ | 2023-09-27 00:37 | - |
| PLD/ | 2023-09-27 00:38 | - |
| Projects/ | 2023-09-27 00:38 | - |
| Reverse Engineering/ | 2023-09-27 00:38 | - |
| ROM/ | 2023-09-27 00:38 | - |
| Sockets/ | 2023-09-27 00:38 | - |
| Sound/ | 2023-09-27 00:39 | - |
| Speech/ | 2023-09-27 00:39 | - |
| Static RAM/ | 2023-09-27 00:39 | - |
| Voltage Regulator/ | 2023-09-27 00:39 | - |
| Xilinx ISE Stuff/ | 2023-09-27 00:53 | - |
![[ ]](/theme/icons/doc.png){kind=icon} | Capacitor Values.doc | 2020-04-05 13:23 | 36K |
| Logic Symbols.doc | 2020-04-05 13:23 | 58K |
![[ ]](/theme/icons/pdf.png){kind=icon} | DRAM and Resistors Networks - Ringing Issues Explained.pdf | 2020-04-05 13:19 | 82K |
![[ ]](/theme/icons/zip.png){kind=icon} | Electronics.zip | 2020-04-05 13:22 | 375M |